CMOS Resistance: Drawing NAND & Solutions

In summary, when both A and B are high (value 1), the resistance will be Rn + Rn as the two NMOS are in series. When both A and B are low (value 0), both PMOS will be turned on and the resistance will be Rp/2 as they are in parallel. When A is high and B is low, the resistance will only be Rp as they are neither in series nor parallel.
  • #1
nobrainer612
26
0

Homework Statement



I drew a NAND in the picture.

302tlld.jpg




The Attempt at a Solution



I know when A and B are both high ( value 1), resistance will be Rn + Rn because those 2 NMOS will be turned on and resistance will added up since they are in series.

Also when A and B are both low ( value 0), both PMOS will be turned on. My first question is, 1.) is the resistance become Rp*Rp/(Rp + Rp) because they are in parallel?

My second question is, if A is high (value 1) and B is low ( value 0) , output should be VDD ( value 1). But what will be resistance be? I think they are neither in series nor parallel. So will the resistance only become Rp ?

Hope somebody can share their ideas. Thank you
 
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  • #2
nobrainer612 said:
I know when A and B are both high ( value 1), resistance will be Rn + Rn because those 2 NMOS will be turned on and resistance will added up since they are in series.

Also when A and B are both low ( value 0), both PMOS will be turned on. My first question is, 1.) is the resistance become Rp*Rp/(Rp + Rp) because they are in parallel?

My second question is, if A is high (value 1) and B is low ( value 0) , output should be VDD ( value 1). But what will be resistance be? I think they are neither in series nor parallel. So will the resistance only become Rp ?

Hope somebody can share their ideas. Thank you
Hi nobrainer612! Those would be my answers, too.

Can you simplify this expression: Rp*Rp/(Rp + Rp) :wink:
 
  • #3
sorry but I don't get what you mean.

Can you tell me if those I assumed are correct? because I am interested what the resistance is .

simplify this expression: Rp*Rp/(Rp + Rp) : isn't that equal (Rp^2) / 2*Rp = Rp/2?


So what I assumed:

if A is high (value 1) and B is low ( value 0) -----> resistance = Rp only? :bugeye:
Also when A and B are both low ( value 0) -----> resistance = Rp/2 ? :shy:
 
Last edited:
  • #4
nobrainer612 said:
if A is high (value 1) and B is low ( value 0) -----> resistance = Rp only?
Also when A and B are both low ( value 0) -----> resistance = Rp/2?
:smile:
 
  • #5


I appreciate your attempt at drawing the NAND and your understanding of the resistance values when A and B are both high or low. To answer your first question, yes, when both PMOS are turned on, the resistance will become Rp*Rp/(Rp + Rp) since they are in parallel.

For your second question, the resistance will indeed only become Rp when A is high and B is low, as they are not in series or parallel. This is because the PMOS on the bottom will be turned off, so the only resistance in the circuit will be from the top PMOS.

I would also like to add that in CMOS circuits, the resistance values are not constant and can vary depending on the input voltage and other parameters. It would be helpful to consider these factors in your analysis. Overall, your understanding of the resistance values in a NAND circuit is correct and I encourage you to continue exploring and learning more about CMOS circuits.
 

Related to CMOS Resistance: Drawing NAND & Solutions

What is CMOS resistance?

CMOS resistance is a measure of how well a CMOS (complementary metal-oxide-semiconductor) device can maintain its resistance while being used in a circuit. It is an important consideration when designing and using CMOS devices in electronic circuits.

Why is CMOS resistance important in drawing NAND?

CMOS resistance is important in drawing NAND because it affects the overall performance and reliability of the circuit. Too high or too low resistance can lead to errors or malfunctions in the circuit. Drawing NAND with the correct CMOS resistance ensures proper functioning of the circuit.

What is the relationship between CMOS resistance and power consumption?

There is an inverse relationship between CMOS resistance and power consumption. Higher resistance leads to lower power consumption, while lower resistance leads to higher power consumption. This is because a higher resistance means less current is flowing through the circuit, resulting in less power being used.

How can CMOS resistance be controlled?

CMOS resistance can be controlled through various methods such as using different materials for the CMOS device, changing the dimensions of the device, or adjusting the doping concentration. It can also be controlled by changing the circuit design or using different biasing techniques.

What are some possible solutions for high CMOS resistance?

If the CMOS resistance is too high, it can be reduced by using a larger device size, increasing the doping concentration, or optimizing the circuit design for lower resistance. It is also important to ensure that the CMOS device is not damaged or degraded in any way, as this can also lead to higher resistance. Replacing the device with a new one may be necessary if it is damaged.

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